As startup companies and major vendors have been aggressively entering AI hardware market mainly in the United States and China, it is an urgent issue in Japan to develop human resources and industry of the hardware market in order to accelerate AI processing including LSI and FPGA as well as software.
In light of such situation, we will hold this contest for the purpose of development of C-based composed HLS introduced as a development of AI hardware - RTL design - LSI development as well as development of startup and industry.

Contest Outline

Subject (Algorithm Development)
Assign a rectangular area including predictive object as bounding box=(x1,y1,x2, y2) toward the image of the vehicle front camera and give one category. More than one bounding boxes are assigned on each image and a bounding box is indicated by specifying 4 points of the top left coordinates (x1, y1) and bottom right coordinates (x2, y2) in the object area as the origin (0,0) on the top left coordinates on the image.
Predictive target objects are following 6 categories.
・Car
・Truck
・Pedestrian
・Bicycle
・Signal
・Signs

Subject (Algorithm Implementation)
Implement developed algorithm into Avnet Ultra96 (Zynq UltraScale+ MPSoC ZAU3EG SBVA484) FPGA board. We plan to provide FPGA board to a maximum of 80 applicants based on the review of application among the people who apply through application form for the board offer document review. Please apply from the button below if you would like to get the FPGA board offer to use for this contest.

Application Form for Board Offer Document Review

Data
Route：Tokyo Route1 (Shibuya - Haneda), Tokyo Route2 (Kagurazaka), Saitama Route (Bijogi)
Time of day：Morning/Daytime/Night (Only Daytime for Tokyo Route2 (Kagurazaka))
Shooting interval：One second (*There are some exceptions.)
Resolution：1936 x 1216
Number of Images：(For Train) 21,258 images, (For Test) 6,355 images
Number of Categories：10
Category Types：Passenger Car (Car), Pedestrian (Pedestrian), Truck (Truck), Signal (Signal), Signs (Signs), Bicycle (Bicycle), Motorbike (Motorbike), Bus (Bus), Special Vehicle (Svehicle), Train (Train)

Travel Route
Tokyo Route 1 (Shibuya - Haneda)　　　　　　　　　　　　　Saitama Route (Bijogi)

Flow of entry / registration for the contest
1. Sign up for SIGNATE (Please register through the member registration button on the top right of the page if you are not currently a member.).
2. Download the data from the data tab (Please agree the terms of entry that will be displayed when downloading.).
3. Prepare the Ultra96-V2 board (if you do not have one, you can purchase it by yourself or apply through the application form for the board offer document review on the website.).
4. Algorithm development, FPGA implementation and optimization.
5. Check the Precision by posting predictive result through the post button.
6. Submit the set of final result by the end of the contest.(application form has been set up at the bottom of the data page.)

Reference information for obtaining the Ultra96 board to use for this contest

・Subjected board for this contest is Ultra96-V2.
・Regarding method to obtain: There are two ways to obtain it.

1. Provided from this contest
- Although limited in number, the Ultra96 board will be provided after review for the contest participants. For those of you who wish to be provided, please apply through the "application form for board offer document review".
- Provided board includes an AC adapter, power conversion cable, and JTAG board.

2. Obtain from the Avnet website
- You can purchase from here.
- We recommend you to purchase the following related parts along the purchasing of the board.
・JTAG board for Ultra96: It is necessary to connect the UART (serial) consol.
・Avnet recommended AC adapter, power conversion cable
　- Power supply
　- Conversion connector

Regarding the errata of Ultra96 board
The errata from Avnet is published the following site.
http://avnet.me/Ultra96-V2_Errata

The errata particularly has the following known issues:
・Reboot issue of Ultra96-V2
　- Ultra96-V2 When the load of the PL part goes up high, MPSoC reboots.
　- Ultra96-V2 It is posted on the errata reporting page.
This is caused by the reset operation in MPSoC that was triggered by the PowerGood signal's drop when a specific threshold is exceeded while the IC called PMIC is monitoring the Vccint voltage.
- There is no margin for this threshold setting in the current V2 board, and a reset is applied when a set threshold is exceeded due to increase in current consumption of the PL section.
- The limit is 3A for the current ULtra96v2.

・The limit of this errata can be relieved to about 5A by revising the board and changing the setting of PMIC. A complete set of countermeasure procedures prepared by Avnet can be downloaded from below.
　20191114_Ultra96-V2 PMIC update procedure.zip (This can be obtained by the data tab on this website)
　Infinion that is required for the measures of this issue.
　The sales information of USB005 writing cable is as follows.
　Mouser
　Digikey
　Chip1Stop

・We plan to provide this revised board for the board offered from this contest.

FPGA seminar for AI edge contest

In conducting the FPGA implementation contest of the AI edge contest, we held a seminar on edge deep learning processing using FPGA for software and AI engineers who are interested in hardware implementation such as FPGA, and applied for the contest. Aim to accelerate human resource development through contest application, along with providing opportunities.

Overview
Date: 13:30-17:00, Tuesday, February 18 (Reception starts at 13:00-)
Location: Innotec Building 2F Seminar Room
agenda:
13:00: Venue open
13: 30-13: 50 (20min) Opening remarks and introduction of the contest (Saito of NEDO, Obuchi of Digital Media Professional)
13: 50-14: 35 (45min) FPGA Seminar # 1 (Koyama of FPGA Information)
14: 35-14: 50 (15min) break
14: 50-15: 35 (45min) ML learning platform of Google Cloud to be used in AI edge development (Sato of Google)
15: 35-16: 50 (75min) FPGA seminar # 2 (Koyama of FPGA Information)
16: 50-17: 00 (10min) Wrap-up, Q&A throughout (Obuchi of Digital Media Professional)

Information for the day
Reception desk: Innotek Building 1F (3-17-6 Shin-Yokohama, Kohoku-ku, Yokohama 222-8580)
Reception start time: 13:00, Tuesday, February 18
Reception method:
Please receive the "Building Admission Sticker" at the dedicated reception on the right side of the 1F front entrance, and go up to the 2nd floor using the entrance stairs.
Please give your reception number in the front room of the 2F seminar room. Please hand one business card at that time. (If you do not have a business card, please let us know.)

FPGA Seminar Participation Application Form

Evaluation method
[Precision] Evaluated by evaluation function "MAP@loU=0.75".
[Processing performance (fps)] Average inference time per sheet
[Area] Composed Report

Decision method of winners
1) Applicants whose Precision evaluation (final evaluation) of the predictive results posted during the contest period meet the Precision criteria 0.15 can be candidates for winners.(You can download a sample of the trained network based on Tiny Yolo v3, which is the basis for setting the accuracy standard, from the data page)
*The information of the precision criteria based on the original Tiny Yolo's network will be provided (provisional precision values) by the beginning of December, and the final required precision will be confirmed by the end of the year.
*The precision can be checked by using the submitting function of this website even during the contest, and evaluation after the contest ends (final evaluation) is adopted for the precision evaluation.

Evaluation until the final day of the contest (provisional evaluation) is performed by a part of the evaluation data set, and evaluation after the contest (final evaluation) is performed by the remaining part of the evaluation data set.

The leaderboard automatically switches to the final evaluation at the end of the contest. For this reason, rankings may vary greatly between during and after the event.

2) Among the winning candidates who meet the precision criteria and submit (application form has been set up at the bottom of the data page) a set of final results (including processing performance (average inference time per sheet) and the information of the FPGA implementation area) by the end of the contest (submission deadline), the top five people with the highest processing performance (plus those whose reports are worthy of attention) will be invited to the Review Committee.
The section where the processing time should be measured is "the time from performing inference processing on the image data already loaded on the memory, and then converting it to information equivalent to JSON such as dict".

3) The winners (best performance award and special award) are determined based on the processing performance, the content of the demo each brought in, the points of ingenuity (refer to this section for the area information) at the Review Committee.

Evaluation function of Precision
・The evaluation function MAP @ IoU = 0.75 will be used.
・An evaluation value between 0 and 1 will be assigned. The higher the accuracy, the higher the value will be.
・Please refer to the evaluation function that can be downloaded on the data page

Details of Evaluation function of Precision
1.For test images, if the IoU for the overlap of ground truth and prediction areas is 0.75 or greater, area detection is considered to have been successful.
2.For test images, average precision (AP) will calculated in each prediction category for objects in each detection area.
3.For each test image, mean average precision (MAP) calculation will be carried out for all eligible prediction categories based on step 2 results.
4.MAP, as calculated in step 3, will be calculated for all test images.

Comprehensive Ranking
・This competition is not subject to SIGNATE's comprehensive ranking (score and medal).

Use of System
・Only one account can be assigned to one person. However one account can be assigned to a team as well. If you want to participate as a team, please read here to create a team. (Deadline to create a team: December 31, 2019 (Tuesday))

Information Handling
・Sharing of data and source code related to the prediction of this contest with participants other than the same team shall be prohibited.
・However, it can be shared only if it is open to all participants in this contest forum.

Use of Data
・Use of data other than provided data, learned models, API, etc. shall not be restricted as long as the method allows verification of reproducibility without charge.
・For example, modification of learning data (including manual labeling and label rewriting) shall be allowed.

Host：Ministry of Economy, Trade and Industry / New Energy and Industrial Technology Development Organization (NEDO)

Co-host：Digital Media Professionals Inc. / SIGNATE Inc.

Support：IEEE Japan Office / IEICE Technical Committee on Reconfigurable Systems (RECONF) / Japan Electronics and Information Technology Industries Association (JEITA) / The Institute of Electronics, Information and Communication Engineers (IEICE) / The Society of Instrument and Control Engineers (SICE) / The Robotics Society of Japan (RSJ) / Society of Automotive Engineers of Japan, Inc. / The Japanese Society for Artificial Intelligence (JSAI) / The Japan Society for Precision Engineering

Sponsor：Sompo Japan Nipponkoa Insurance Inc. / Mitsubishi Electric Corporation / Panasonic Corporation / Digital Media Professionals Inc. / Dynamic Map Platform Co., Ltd. / DENSO Corporation / NEC Corporation / Google Japan LLC / Tier IV, Inc. / SAKURA Internet Inc. / Sony Corporation / SoftBank Corp. / Renesas Electronics Corporation / Informa Intelligence G.K. / Morpho, Inc. / Toyota Research Institute Advanced Development, Inc.

Steering Committee Members
Shinpei Kato　Tokyo University
Kohei Ozaki　Algotechnica LLC
Atsuto Suyama　SB Drive Corp.
Naoki Suganuma　Kanazawa University
Yutaka Sato　National Institute of Advanced Industrial Science and Technology
Hiroaki Kitano　Sony Computer Science Laboratories
Hiroaki Matsumoto　Sony Semiconductor Solutions Corporation
Hironobu Tanba　SoftBank Corporation
Hironobu Fujiyoshi　Chubu University
Hiroki Nakahara　Tokyo Institute of Technology
Yoshiki Ninomiya　Nagoya University
Hirokazu Nishio　Mitou Foundation
Masaki Hiraga　Morpho, Inc.

▼ Special Contract on this Contest
In accordance with Article III “Prizes and Rights” of the special regulations established for this contest as described below, participants will either choose to make their own submission data, source code and other relevant items be licensed under an Open Source Initiative approved license (www.opensource.org) or not. This license imposes no restrictions on commercial use for licensed models, source code, and any results attained using said source code. Incidentally, the participants who will not choose this license will not be able to prize winner candidate, even though they can participate in the contest. In regard to posting and/or other publication on any social media site, blog or similar by the participant of information relating to any algorithm developed by said participant or any other materials produced for or related to this contest (including materials used for final submissions and/or final evaluations/inspections), no restrictions apply to posting and/or publication as long as the participant clearly explains that the posted/published items relate to this contest, and absolutely posts the positing and/or publication information (including the link URL to the pages) on the contest forum in order to let all the participants know it.